1. Field of the Invention
The present invention relates to a nonvolatile memory control circuit mainly for an electrically erasable nonvolatile memory.
2. Description of the Prior Art
FIG. 14 illustrates in block form a conventional nonvolatile memory control circuit. In FIG. 14, reference to numeral 1 denotes a memory cell of an electrically erasable nonvolatile memory such as a flash memory, 2 a word decoder for decoding word lines that select addresses of the memory cell 1 in the horizontal direction, 3 a selector decoder for decoding a bit line selector 4 that selects addresses of the memory cell 1 in the vertical direction, and 4 the bit line selector that selects a bit line based on a selector decode signal from the selector decoder 3.
Reference numeral 5 denotes a data bus, 6 an address bus, 7 a data latch for latching a memory control command to be sent to the data bus 5 and data to be written in the memory cell, 8 an address latch for latching an address signal that specifies the address of the memory cell 2 for reading or writing it, 9 a write/read/erase control circuit for controlling a data write, read or erase operation of the memory cell 1, 10 a data bus, 11 an address bus, 12 an address latch signal generator that generates an address latch signal for latching an address signal on the address bus 6 in the address latch 8, 13 a signal line that conveys the address latch signal, 14 selector decode lines each for conveying the selector decode signal from the selector decoder 3, and 15 word decode lines each for conveying a word decode signal from the word decoder 2.
Reference numeral 16 denotes a chip enable signal generator for generating a chip enable signal CE that enables the nonvolatile memory control circuit to operate, 17 a signal line for conveying the chip enable signal CE from the chip enable signal generator 16, 18 an output enable signal generator for generating an output enable signal OE that enables data read out of the memory cell 1 to be provided onto the data bus 5 via the write/read/erase control circuit 9, 19 a signal line for conveying the output enable signal OE, 20 a write enable signal generator for generating a write enable signal WE for latching command data that is input into the nonvolatile memory control circuit from the outside or data to be written in the memory cell 1, and 21 a signal line for conveying the write enable signal WE. Reference numeral 22 denotes a command latch for latching command data on the data bus 10, 23 a data bus, 24 a command decoder for deciding whether the command data input via the data bus 23 is a write, read or erase command, 25 a write signal generator for generating a write signal for writing data in the memory cell 1, 26 a read signal generator for generating a read signal for reading out data from the memory cell 1, 27 an erase signal generator for generating an erase signal for erasing data on the memory cell 1, 28, 29 and 30 signal lines each for conveying a command decode signal from the command decoder 24, and 31, 32 and 33 signal lines for conveying the write signal, the read signal and the erase signal, respectively.
Reference numeral 34 a clock generator/frequency demultiplier for generating a clock on which the write/read/erase operation of the memory cell 1 is based, 35 and 36 signal lines for conveying the clock, 37 a command latch signal generator for generating a command latch signal, and 38 a signal line for conveying the command latch signal.
The operation of the conventional nonvolatile memory control circuit will be described below.
FIG. 15 is a timing chart showing the timing for writing data in the memory cell 1 of the traditional nonvolatile memory control circuit depicted in FIG. 14. In FIG. 15, reference numeral 39 indicates the command latch signal that is output onto the signal line 38 from the command latch signal generator 37, and 40 the address latch signal that is provided onto the signal line 13 from the address latch signal generator 12.
A data write to the memory cell 1 is carried out in two steps of processing the-write command (a first cycle) and write data (a second cycle) both provided onto the data bus 5. More specifically, the command input operation in the first cycle begins with changing the chip enable signal CE on the signal line 17 from a logical value "1" to "0" and the write enable signal WE on the signal line 21 from a logical value "1" to "0." By this, the write/read/erase control circuit 9 goes into a command input waiting state. Next, command data "40H" (H representing the hexadecimal notation) for the write operation is input into the nonvolatile memory control circuit from the outside thereof and the write enable signal WE is changed from the logical value "0" to "1." As a result, the command latch signal 39 is provided onto the signal line 38 and the command latch 22 latches the command data "40H." The command latch signal 39 is output by one pulse only at this timing in the first cycle. Upon latching of the command data, the command decoder 24 decodes the command data and raises the write command decode signal on the signal line 28 up to the logical value "1." And the chip enable signal CE on the signal line 17 is raised from the logical value "0" to "1." Thus the command input operation of the first cycle is completed. This is followed by the second cycle operation of inputting write address data and write data. For example, in the case of writing data "00H" in the memory cell 1 at an address "4000H," an address signal "4000H" is input onto the address bus 6 from the outside and the chip enable signal CE on the signal line 17 and the write enable signal WE on the signal line 21 are each changed from the logical value "1" to "0". By this, when the write enable signal WE goes down to the logical value "0," the address latch signal 40 is provided onto the signal 13 from the address latch signal generator 12 and the write address of the memory cell 1 is latched in the address latch 8. At the point in time that the address signal "4000H" is input onto the address bus 6, the selector decode line 14 and the word decode line 15 are both already at the logical level "1" and the selection of these lines is determined at the point when the address latch signal 40 is output.
Next, the write data "00H" is input onto the data bus 5 from the outside. By changing the write enable signal WE from the logical value "0" to "1," the data "00H" is latched in the data latch 7. When the write address and the write data are latched in the address latch 8 and the data latch 7, respectively, a write signal is output onto the signal line 31 from the write signal generator 25 and at the same time a signal is provided on the signal line 35 to activate the clock generator/frequency demultiplier 34. Since the decode signals on the selector decode line 14 and the word decode line 15 corresponding to the address "4000H" are already at the logical level "1," the data "00H" is stored in the memory 1 at the address "4000H." The write signal goes down to the logical level "0" when the number of clock signals provided onto the signal line 36 from the clock generator/frequency demultiplier 34, counted by the write signal generator 25, reaches a predetermined value.
FIG. 16 is a timing chart that depicts the timing for reading out data from the memory cell 1 in the conventional nonvolatile memory control circuit shown in FIG. 14. As is the case with the data write, the command input for the data read operation is carried out only in the first one cycle.
The data read procedure begins with forcing the chip enable signal CE to the logical level "0," putting the write/read/erase control circuit 9 in the input waiting state. Then the write enable signal WE goes to the logical level "0," enabling read command data "10H" to be input onto the data bus 10 via the data latch 7 and output onto the data bus 23 via the command latch 22.
After this, when the write enable signal WE rises to the logical level "1," the command latch signal generator 37 generates the command latch signal 39, latching the read command data "10H" in the command latch 22. The command decoder 24 generates a signal of the logical level "1" onto the signal line when it decides that the data provided on to the data bus 23 is read command. The read signal generator 26 receives the signal on the signal line 29 and generates a read request signal of the logical level "1" onto the signal line 32. The write/read/erase control circuit 9 is switched by the read request signal into a read control state.
Thereafter, the address data "4000H" is input onto the address bus 6 and then output onto the address bus 11 after being once latched in the address latch 8. At a point in time the chip enable signal CE goes down to the logical level "0," the signal levels on the selector data code line 14 and the word decode line 15 corresponding to the address "4000H" are made high by the word decoder 2, the selector decoder 3 and the bit line selector 4. Following this, the output enable signal OE on the signal line 19 goes down to the logical level "0" and the write/read/erase control circuit begins the read operation. Thus the data stored in the memory cell 1 at the address "4000H" is read out therefrom and provided onto the data bus 5.
FIG. 17 is a timing chart that depicts the timing for erasing data from the memory cell 1. In FIG. 17, reference numeral 41 denotes a command latch signal that is provided onto the signal line 38 from the command latch signal generator 37 in the second cycle.
The erase operation executed by performing a data latch of two cycles at the same timing as in the write operation. A first step of the erase procedure consists of latching erase command data "20H" in the command latch 22 in the command input operation of the first cycle. The next step is to latch again the erase data "20H" in the command latch 22 in the command input operation of the second cycle. In consequence, the erase signal generator 27, which has received the decode signal provided twice in succession onto the signal line 30 from the command decoder 24, generates an erase signal onto the signal line 33. By this, the memory cell 1 is erased over the entire storage area thereof. The erase signal on the signal line 33 goes down to the logical level to "0" when the number of clock signals on the signal line 36 provided from the clock generator/frequency demultiplier 34, counted by the erase signal generator 27, reaches a predetermined value.
Since the conventional nonvolatile memory control circuit has such a configuration as described above, anyone can write, read or erase data if he or she follows a fixed procedure to enter a preset write, read or erase command. On the other hand, since anyone can erase data written in the memory cell, there is a fear of important data or programs stored in the memory cell being readily erased by a third party.